module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
); //

    // You may use these parameters to access state bits using e.g., state[B2] instead of state[6].
    //parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;

    // assign B3_next = ...;
    // assign S_next = ...;
    // etc.

    localparam FSM_W  = 10;
    localparam FSM_W1 = FSM_W - 1'b1;

    reg [FSM_W1:0]   nxt_state;

    localparam  S_0         = 0;
    localparam  S_1         = 1;
    localparam  S_11        = 2;
    localparam  S_110       = 3;
    localparam  B0          = 4;
    localparam  B1          = 5;
    localparam  B2          = 6;
    localparam  B3          = 7;
    localparam  WAT_CNT_FIN = 8;
    localparam  WAT_ACK     = 9;

    always @(*) begin
        nxt_state[S_0    ]          =   (state[S_1    ] && ~d) || (state[S_0    ] && ~d) 
                            || (state[S_110   ] && ~d) || (state[WAT_ACK       ] && ack);
        nxt_state[S_1    ]          =   (state[S_0    ] &&  d);
        nxt_state[S_11   ]          =   (state[S_1    ] &&  d) || (state[S_11   ] &&  d);
        nxt_state[S_110  ]          =   (state[S_11   ] && ~d);
        nxt_state[B0     ]          =   (state[S_110  ] &&  d);
        nxt_state[B1     ]          =   (state[B0     ]);
        nxt_state[B2     ]          =   (state[B1     ]);
        nxt_state[B3     ]          =   (state[B2     ]);

        nxt_state[WAT_CNT_FIN   ]   =   state[B3]
                                    || (state[WAT_CNT_FIN   ] && ~done_counting);

        nxt_state[WAT_ACK       ]   =   (state[WAT_CNT_FIN   ] && done_counting) 
                                    || (state[WAT_ACK       ] && ~ack);
    end

    assign          B3_next         =   nxt_state[B3];
    assign          S_next          =   nxt_state[S_0];
    assign          S1_next         =   nxt_state[S_1];
    assign          Count_next      =   nxt_state[WAT_CNT_FIN];
    assign          Wait_next       =   nxt_state[WAT_ACK];
    assign          done            =   state[WAT_ACK] ;
    assign          counting        =   state[WAT_CNT_FIN];
    assign          shift_ena       =   state[B0] 
                                    ||  state[B1]
                                    ||  state[B2]
                                    ||  state[B3];

endmodule
